| 姓名 | 黃逸豪(Yi-Hao Huang) | 電子郵件信箱 | E-mail 資料不公開 |
| 畢業系所 | 電子工程系(Department of Electronic Engineering) | ||
| 畢業學位 | 碩士(Master) | 畢業時期 | 97學年第2學期 |
| 論文名稱(中) | 雙材質閘極具高低基體摻雜與氧化層基體絕緣結構之金氧半場效電晶體次臨界行為分析 | ||
| 論文名稱(英) | The Investigation on Subthreshold Behavior Model for Single-Halo Dual-Material Gate SOI MOSFETs | ||
| 檔案 |  沒有電子論文檔案
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論文使用權限 | 校內校外均不公開 |
| 論文語文/頁數 | 英文/84 | ||
| 統計 | 本論文已被瀏覽 171 次，被下載 0 次 | ||
| 摘要(中) | 近年來雙材質閘極(Dual-material gate)具高低基體摻雜(Single halo)與氧化層基體絕緣結構(SOI)之金氧半場效電晶體已引起元件工程師之注意與研究，和傳統的單閘極(Single-material gate)金氧半場效電晶體(MOSFET)相較，雙材質閘極電晶體在尺度的微縮上具有較大的空間與優勢，更符合目前電子電路設計傾向奈米級尺寸之需求。除此之外，雙閘極高低基體摻雜(Single halo)與氧化層基體絕緣結構(SOI)之金氧半場效電晶體具有較佳之短通道特性，因此雙閘極高低基體摻雜(Single halo)與氧化層基體絕緣結構(SOI)之金氧半場效電晶體應用在數位電路上是不錯的選。 本論文乃基於雙材質閘極具高低基體摻雜與氧化層基體絕緣結構之金氧半場效電晶體帕森方程式之完全封閉型解，成功地推導出次臨界行為之分析模型，此模型不僅準確顯示出電位分佈、電場分佈、短通道臨界電壓縮減、次臨界電流、次臨界斜率、汲極偏壓引致通道位能障降低等效應，並且此模型之演算結果與模擬數據相當接近，此元件可有效降低熱載子效應，減緩臨界電壓下滑，減少汲極偏壓引致通道位能障降低，以及增加載子傳輸效應，並可提供基本之元件庫，進而被廣泛應用於積體電路之模擬。 | ||
| 摘要(英) | In recent years，Single-halo Dual-material gate (SHDMG) Silicon-on-insulator (SOI) Material Oxide Semiconductor Field Effect (MOSFET’s) have attracted a lot of device engineer attention. Compared with convention single- material gate, Dual-material gate (DMG) MOSFET’s have more great performance because of using dual-material on the front gate to produce the step to suppress hot carrier effect (HCE). DMG MOSFET have more space and advantage in the scale length, therefore the device conform circuit design with nanometer regime. Besides, Single-halo Dual-material gate SOI MOSFET’s is a great choose on the digital electric circuit application. In this thesis, on the basis of the exact solution of the two-dimensional Poisson equation, a new analytical model of subthreshold behavior for the single-halo, dual-material gate (SHDMG) silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is developed. The model is verified by the good agreement with a numerical simulation using the device simulator MEDICI. The SHDMG SOI MOSFET’s have been to Reduced the hot-carrier effect, decrease the DIBL effect, efficient alleviate the degradation of the threshold voltage and Increase the device speed. The model not only offers the physical insight into device physics but also provides the efficient device model for circuit simulation. | ||
| 關鍵字(中) | 關鍵字(英) | ||
| 論文目次 | 摘要 i Abstract ii Acknowledgements iii Contents ix List of Figures vii Chapter 1 Introduction 1 1.1 MOSFET Overview 1 1.2 Single-Halo Dual Material Gate SOI MOSFETs 2 1.3 Motive of the Thesis 5 Chapter 2 Two Dimensional Model for Single-Halo Dual Material Gate SOI MOSFET’s 6 2.1 Model Derivation 6 2.2 2D Boundary Conditions Value Problem 8 2.3 1D Solution 10 2.4 Coefficients Solution 12 2.5 2D Generalized Potential Model 16 2.6 Minimum Channel Potential 19 2.7 Electric Field and Potential Contour 21 2.8 Physical Threshold Voltage Roll-off Model 24 2.9 The Definition Minimum Channel Length 29 2.10 Results and Discussion 30 Chapter 3 Two Dimensional Subthreshold Behavior Model for Single-Halo Dual-Material Gate SOI MOSFET’s 31 3.1 Subthreshold Current Model 31 3.2 Subthreshold Slope Model 35 3.3 Results and Discussion 38 Chapter 4 The Subthreshold Behavior Model Single-Halo Dual-Material Gate SOI MOSFETs: By Considering Effective Substrate Bias effects 39 4.1 Motive 39 4.2 Two Dimensional Potential 40 4.3 Threshold Voltage 48 4.4 Subthreshold Behavior 53 4.5 Results and Discussion 58 Chapter 5 Conclusions and Future Works 59 5.1 Conclusions 59 5.2 Future Works 59 Publications List 61 References 62 Introduction of the Author 67 | ||
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| 口試日期 | 0000-00-00 | 繳交日期 | 2009-07-28 |